1. Field of the Invention
The invention relates to a delay locked loop (DLL) circuit for providing an adjustable phase relationship with respect to a periodic input signal.
2. Description of the Related Art
DLL circuits are generally used in integrated circuits to derive a clock signal from a reference clock signal with a particular defined phase relationship. A conventional DLL circuit (as is used, for example, in integrated circuits) has delay elements which are arranged in a row and form a delay chain. A periodic input signal, preferably the reference clock signal, is applied to the input of the first delay element in the delay chain. The delay time of the delay elements can be adjusted on the basis of an item of control information. A phase detector compares the phase relationship of the reference clock signal at the input of the delay chain with that of a signal (which has been phase-shifted with respect to said reference clock signal) at the output of the delay chain, i.e., at the output of the last delay element in the delay chain. If there is a phase difference, an item of control information is generated in order to adjust the delay time of the individual delay elements.
Such a DLL loop is usually adjusted in such a manner that the delay chain gives rise to a phase shift of 180°, with the result that the delay time or the phase shift of each delay element is given by a phase shift of 180° divided by the number of delay elements in the delay chain. The outputs of the delay elements are connected to a selection element which selects one of the outputs of the delay elements on the basis of a selection signal which has been provided and outputs the output from the selected delay element to an output line of the DLL circuit. The selection signal corresponds to a desired phase shift of the input signal with respect to a periodic output signal and specifies the number of delay elements through which the reference clock signal is intended to pass between the input line and the output line of the DLL circuit. If phase shifts of between 180° and 360° are required, the selection element can additionally invert the output signal from the relevant delay element in accordance with the selection signal.
On account of the regulation of the feedback loop, all variations in the process parameters, the operating voltage or the temperature which influence the delay time of the delay elements, insofar as they influence the phase shift of the entire delay chain, are compensated for. However, the DLL circuit usually contains further elements which are not compensated for by regulation and which give rise to an additional delay of the reference clock signal, namely an input buffer for the delay chain, which is provided in order to provide the delay chain with an input signal with a defined driver strength, and the selection element, which likewise has a signal delay. A phase shift of greater than 0° therefore exists between the periodic input signal and the periodic output signal from the DLL circuit even if a desired phase shift of 0° is selected in the selection element.